1. Field of the Invention
The invention relates to the field of parallelization of programs. More particularly, the present invention relates to a method for speeding up a simulation system through parallel execution of a program.
2. Description of the Related Art
Recently, multiprocessor systems with a plurality of processors have been used in fields such as scientific computing and simulation. In these systems, application programs generate a plurality of processes, and these processes are allocated to individual processors and executed.
In the field of simulation, which has seen extensive development in recent years, there is software for mechatronic “plant” simulations of robots, automobiles and airplanes. Due to the development of electronic components and software technology, most of the controls are performed electronically using wires and wireless LAN configured like the nerves of a robot, automobile, or airplane.
A large amount of control software is built into mechanical devices. When these products are developed, there is an extensive length of time, an enormous cost, and a large number of personnel required for development and testing of the programs.
The method commonly used in testing is “hardware in the loop simulation” (HILS). The environment used to test the electronic control unit (ECU) for an entire automobile is called a full-vehicle HILS. In a full-vehicle HILS, the actual ECU itself is connected to a dedicated hardware device used to emulate an engine or transmission in a laboratory, and testing is performed in accordance with predetermined scenarios. The output from the ECU is inputted to a monitoring computer, and displayed so that testing personnel can check for anomalous behavior while viewing the display.
However, because a dedicated hardware apparatus is used and physical wiring is required between the device and the actual ECU, the amount of preparation required for HILS is extensive. Also, replacement and testing of another ECU requires a large amount of time because physical reconnection is required. In addition, because the actual ECU is tested, the testing has to be performed in real time. Therefore, an enormous amount of time is required when many scenarios are tested. Also, hardware devices for HILS emulation are generally very expensive.
Recently, a method consisting of software which does not require an expensive hardware device for emulation has been proposed. This method is known as “software in the loop simulation” (SILS). Using this method, the microcomputer mounted in the ECU, the input/output circuit, the control scenario, and the plant, such as an engine or a transmission, all consist of a software emulator. This can even be used to perform testing without the ECU hardware.
A system that can be used to help build a SILS is MATLAB®/Simulink®, which is a simulation modeling system available from MathWorks®. When MATLAB®/Simulink® is used, a simulation program can be created by arranging functional blocks on a screen using a graphical interface, and the processing flow is indicated by connecting the function blocks to each other using arrows. These block diagrams represent the processing performed in the simulation during a single time step. By repeating this a predetermined number of times, the behavior of the simulated system can be obtained in a time series.
When a block diagram with function blocks has been created using MATLAB®/Simulink®, the equivalent functions can be converted to source code in an existing computer language, such as C. This can be accomplished using, for example, Real-Time Workshop® functions. By compiling the source code in C, a simulation can be executed as a SILS in another computer system.
As multiprocessor and multicore computer systems have become more widely available, technologies have been proposed to speed up execution of a program written using block diagrams by dividing the program into groups known as segments, and then allocating these segments to different processors or cores for parallel execution.
In U.S. Patent App. Publication No. 2011/0107162, the counterpart of Japanese Patent No. 4,886,838, when, in a block diagram, output from a function block without an internal state is used by function block A with an internal state, function block A is called a use block of the function block without an internal state. When output from function block A with an internal state is used as input for a function block without an internal state in a calculation, function block A is called a definition block of the function block without an internal state. By visiting each function block as a node, the number of use block sets/definition block sets can be determined for each function block on the basis of the connection relationship between the function blocks with an internal state and function blocks without an internal state. Strands can be allocated on the basis of this number, enabling the block diagram to be divided into strands for parallel processing.
From the perspective of a method for solving this numerically, models written using block diagrams can resemble expressions of an explicit simultaneous ordinary differential equation in state-space form. From this perspective, Kasahara Hironori, Fujii Toshihisa, Honda Hiroki, Narita Seinosuke, “Parallel Processing of the Solution of Ordinary Differential Equations Using Static Multiprocessor Scheduling Algorithms”, IPSJ [Information Processing Society of Japan] Journal 28 (10), 1060-1070, Oct. 15, 1987, relates to a parallel processing method for solving explicit ordinary differential equations, and discloses a parallel processing method for solving ordinary differential equations compatible with a variety of granularities which consists of task generation, optimum task scheduling of processors, and machine code generation using scheduling results.